1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to fabricating a transistor having a high-quality gate dielectric with a high dielectric constant. The transistor further includes barrier species incorporated into the channel region as well as the gate dielectric to provide a diffusion barrier.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing undoped polycrystalline silicon ("polysilicon") over a relatively thin layer of silicon dioxide. The polysilicon material is then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are subsequently implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET ("n-channel") transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET ("p-channel") transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate.
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T, necessary to activate the transistor. Several factors contribute to V.sub.T, one of which is the gate-to-substrate capacitance. The higher the gate-to-substrate capacitance, the lower the V.sub.T of a transistor. The value of this capacitance is dependent upon the thickness of the gate dielectric and the relative permittivity of the gate dielectric. Unfortunately, the relative permittivity, or dielectric constant, K, of the gate dielectric limits the amount of gate-to-substrate capacitance that can be achieved when a transistor is in operation. Permittivity, .epsilon., of a material reflects the ability of the material to be polarized by an electric field. The capacitance between two layers of conductive material separated by a dielectric is directly proportional to the permittivity of the dielectric. The permittivity of a material is typically described as its permittivity normalized to the permittivity of a vacuum, .epsilon..sub.o. Hence, the relative permittivity or dielectric constant of a material is defined as: EQU K=.epsilon./.epsilon..sub.o
Silicon dioxide is widely used as the gate dielectric material (or "gate oxide") in semiconductor devices. Silicon dioxide has a relatively low K of approximately 3.7 to 3.8. As such, the minimum value of V.sub.T, and thus the transistor switching speed, must be somewhat related to capacitive coupling between the gate conductor and the substrate.
As mentioned above, the gate-to-substrate capacitance is also affected by the thickness of the gate dielectric. Conventional transistors typically include an ultra-thin gate oxide to increase the gate-to-substrate capacitance, and thereby lower V.sub.T. The value of the gate-to-source voltage, V.sub.GS, required to invert the channel underneath the gate conductor such that a given drive current, I.sub.D, flows between the source and drain regions of the transistor is decreased. Equivalently, the value of I.sub.D for a given value of V.sub.T increases with decreasing gate dielectric thickness. Consequently, the switching speed (from off to on and vice versa) of the logic gates of an integrated circuit employing transistors with narrow gate dielectrics increases, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies). In addition, thin gate dielectrics advantageously control short channel effects by permitting the gate to retain control of the channel charge.
The use of very thin silicon dioxide gate dielectrics, however, may present several potential problems. Thin silicon dioxide films may break down when subjected to an electric field. Particularly, for a gate oxide that is less than 50 angstroms thick, it is probable that when V.sub.GS is equivalent to only 3 V, electrons can pass through the gate oxide by what is known as the quantum mechanical tunneling effect. In this manner, a tunneling current may undesirably form between the semiconductor substrate and the gate conductor, adversely affecting the operability of the device. It is postulated that these electrons may become entrapped within the gate oxide by, e.g., dangling bonds. As a result, a net negative charge density may form in the gate oxide. As the trapped charge accumulates with time, V.sub.T may shift from its design specification. Breakdown of the gate oxide may also occur at even lower values of V.sub.GS, as a result of defects in the gate oxide. Because it is at present difficult to grow very thin gate dielectric oxides precisely and uniformly across a semiconductor substrate and from wafer to wafer, such defects are unfortunately prevalent in relatively thin gate oxides. For example, a thin gate oxide often contains pinholes and/or localized voids due to unevenness at which the oxide grows on a less than perfect silicon lattice. The gate oxide must also be resistant to breakdown and hot-carrier damage. Low breakdown voltages also correlate with high defect density near the surface of the substrate. Further, in p-channel devices, the gate oxide needs to be resistant to penetration by boron at the processing temperatures used after gate doping.
Another factor that may contribute to V.sub.T is the effective channel length of the transistor, L.sub.eff. L.sub.eff is the actual distance between the source-side and drain-side junctions after implantation and subsequent diffusion and is typically less than the physical channel length. Reducing the L.sub.eff of a transistor to below 1.0 .mu.m may lead to deleterious short channel effects ("SCE"). Generally speaking, SCE impacts device operation by, for example, increasing sub-threshold currents. A problem related to SCE and the subthreshold currents associated therewith is the problem of hot-carrier effects ("HCE"). HCE is a phenomenon by which the kinetic energy of the charge carriers (holes or electrons) is increased as the carriers are accelerated through large potential gradients and subsequently become trapped within the gate oxide. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation of a transistor.
More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs that migrate to and become injected within the gate dielectric near the drain junction. Vacancy and interstitial positions within the gate dielectric generally become electron traps, resulting in a net negative charge density within the gate dielectric. Unfortunately, the trapped charge may accumulate over time, causing the transistor threshold voltage to undesirably shift from its design specification. It is known that since hot electrons are more mobile than hot holes, HCE causes a greater threshold skew in NMOS transistors than PMOS transistors. Nonetheless, a PMOS transistor will undergo negative threshold skew if its L.sub.eff is less than, e.g., 0.8 .mu.m.
It would therefore be desirable to develop a technique for fabricating a transistor with increased resistance to short channel effects and hot carrier effects. It would further be desirable to develop a technique for fabricating a transistor with increased gate-to-substrate capacitance that is substantially resistant to gate dielectric breakdown. Fabrication of a relatively thin gate oxide interposed between the gate and the substrate must be avoided. A transistor with the immediately preceding advantages must also switch on and off quickly, thereby providing for high frequency operation of an integrated circuit. The likelihood of forming a tunneling current between the gate dielectric and the gate conductor of the resulting transistor should also be reduced, as should the possibility of electrons becoming trapped within the gate dielectric. Such a transistor should be substantially resistant to threshold skews from the desired value of V.sub.T.